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100 dB Range (10 nA to 1 mA) Logarithmic Converter AD8305*
FEATURES Optimized for Fiber Optic Photodiode Interfacing Measures Current over 5 Decades Law Conformance 0.1 dB from 10 nA to 1 mA Single- or Dual-Supply Operation (3 V to 12 V Total) Full Log-Ratio Capabilities Nominal Slope of 10 mV/dB (200 mV/Decade) Nominal Intercept of 1 nA (Set by External Resistor) Optional Adjustment of Slope and Intercept Complete and Temperature Stable Rapid Response Time for a Given Current Level Miniature 16-Lead Chip Scale Package (LFCSP 3 mm 3 mm) Low Power: ~5 mA Quiescent Current APPLICATIONS Optical Power Measurement Wide Range Baseband Logarithmic Compression Measurement of Current and Voltage Ratios Optical Absorbance Measurement FUNCTIONAL BLOCK DIAGRAM
I PD 0.20 log 10 1nA VP VPOS VRDZ VREF 200k 0.5V IREF V
BIAS
()
VOUT
80k 20k COMM V Q2 - + V 0.5V VNEG 2.5V
BIAS GENERATOR
SCAL 14.2k BFIN VLOG I TEMPERATURE LOG 451 COMPENSATION
BE1
BE2
I
Q1
PD
INPT VSUM
6.69k COMM COMM
GENERAL DESCRIPTION
The AD8305 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between 3 V and 12 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications. The input current, IPD, of 10 nA to 1 mA applied to the INPT pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current (IREF) applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The output of the logarithmic front end is available at pin VLOG. The basic logarithmic slope at this output is nominally 200 mV/ decade (10 mV/dB). Thus, a 100 dB range corresponds to an output change of 1 V. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD8305's voltage reference output of 2.5 V at pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial
*Protected by U.S. Patent No. 4,604,532 and 5,519,308; other patents pending.
8-bit), and the AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network. The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 10 A, provided by a 200 k resistor connected between VREF, at 2.5 V, and the reference input IREF, at 0.5 V. The intercept can be adjusted over a wide range by varying this resistor. The AD8305 can also operate in a logratio mode, with the numerator current applied to INPT and the denominator current applied to IREF. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current sourcing capacity is 25 mA. It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the 10 nA level, the bandwidth of the AD8305 is about 50 kHz, and increases in proportion to IPD up to a maximum value of about 15 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize lowpass filters of up to three poles. The AD8305 is available in a 16-lead LFCSP package and specified for operation from -40C to +85C.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2002 Analog Devices, Inc. All rights reserved.
(V = 5 V, = 0 AD8305-SPECIFICATIONS otherwise Vnoted.)V, T = 25 C, R
P N A
REF
= 200 k , and VRDZ connected to VREF, unless
Parameter INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUT Logarithmic Slope Logarithmic Intercept1 Law Conformance Error Wideband Noise2 Small Signal Bandwidth2 Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional)
Conditions Pin 4, INPT, Pin 3, IREF Flows toward INPT pin Flows toward INPT pin Flows toward IREF pin Internally preset; may be altered by user -40C < TA < +85C VINPT - VSUM, VIREF - VSUM Pin 9, VLOG -40C < TA < +85C -40C < TA < +85C 10 nA < IPD < 1 mA IPD > 1 A IPD > 1 A Limited by VN = 0 V
Min 10 n 10 n 0.46 -20 190 185 0.3 0.1
Typ
Max 1m 10 m 1m 0.54 +20
Unit A A A V mV/C mV mV/dec mV/dec nA nA dB VHz MHz V V k V V mA mV mA M V mA MHz V/s V mA V
0.5 0.015
200 1 0.1 0.7 0.7 1.7 0.01 5 2.5 20 2
210 215 1.7 2.5 0.4
4.375 Pin 2, VREF -40C < TA < +85C Sourcing (grounded load) Load current < 10 mA Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT -20 Flowing out of Pin 10 or 11 RL = 1 k to ground Load current < 10 mA GAIN = 1 0.2 V to 4.8 V output swing Pin 8, VPOS; Pin 6 and Pin 7, VNEG ( VP - VN ) 12 V ( VP - VN ) 12 V 3 -5.5 2.435 2.4
5.625 2.565 2.6
+20 0.4 35 VP - 0.1 0.5 25 15 15 5 5.4 0 12 6.5
NOTES 1 Other values of logarithmic intercept can be achieved by adjusting R REF. 2 Output noise and incremental bandwidth are functions of input current, measure using output buffer connected for GAIN = 1.
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AD8305
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION
16 COMM 15 COMM 14 COMM 13 COMM
PIN 1 INDICATOR
Supply Voltage VP - VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30C/W JA Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C
1
VRDZ 1 VREF 2 IREF 3 INPT 4
12 VOUT 11 SCAL 10 BFIN 9 VLOG
AD8305
TOP VIEW
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 With package die paddle soldered to thermal pad containing nine vias connected to inner and bottom layers.
VSUM 5
ORDERING GUIDE
Model AD8305ACP AD8305ACP-REEL7 AD8305-EVAL
Temperature Range -40C to +85C 7" Tape and Reel Evaluation Board
Package Description 16-Lead LFCSP
Package Option CP-16
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4 5 6, 7 8 9 10 11 12 13-16
Mnemonic VRDZ VREF IREF INPT VSUM VNEG VPOS VLOG BFIN SCAL VOUT COMM
Function Top of a Resistive Divider Network that Offsets VLOG to Position the Intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided. Reference Output Voltage of 2.5 V Accepts (Sinks) Reference Current, IREF Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo current flows into INPT. Guard Pin. Used to shield the INPT current line and used for optional adjustment of the INPT and IREF node potential. Optional Negative Supply, VN. (This pin is usually grounded; for details of usage, see the Applications section). Positive Supply, (VP - VN ) 12 V Output of the Logarithmic Front End Buffer Amplifier Noninverting Input Buffer Amplifier Inverting Input Buffer Output Analog Ground
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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VNEG 6 VNEG 7
VPOS 8
AD8305-Typical Performance Characteristics
1.6 1.4 1.2 1.0 40 C 25 C 85 C TA = 40 C, 0 C, VN = 0V 25 C, 70 C, 85 C
(VP = 5 V, V N = 0 V, R REF = 200 k , T A = 25 C, unless otherwise noted.)
2.0 1.5 1.0 85 C 70 C 0.5 0 -0.5 40 C -1.0 -1.5 -2.0 1n TA = 40 C, 0 C, VN = 0V 25 C, 70 C, 85 C
0.8 0.6 0.4 0.2 0 1n 0C 70 C
ERROR - dB(10mV/dB)
VLOG - V
0C
25 C
10n
100n
1
10 IPD - A
100
1m
10m
10n
100n
1
10 IPD - A
100
1m
10m
TPC 1. VLOG vs. IPD for Multiple Temperatures
TPC 4. Law Conformance Error vs. IPD (at IREF = 10 A) for Multiple Temperatures, Normalized to 25C
1.8 1.6 1.4 1.2 0C 70 C 25 C 85 C 40 C TA = 40 C, 0 C, VN = 0V 25 C, 70 C, 85 C
2.0 1.5 1.0 70 C 0.5 0 -0.5 25 C -1.0 -1.5 -2.0 1n 0C 40 C 85 C TA = 40 C, 0 C, VN = 0V 25 C, 70 C, 85 C
1.0 0.8 0.6 0.4 0.2 0 1n
10n
100n
1
10 IREF - A
100
1m
10m
ERROR - dB(10mV/dB)
VLOG - V
10n
100n
1
10 IREF - A
100
1m
10m
TPC 2. VLOG vs. IREF for Multiple Temperatures
TPC 5. Law Conformance Error vs. IREF (at IPD = 10 A) for Multiple Temperatures, Normalized to 25C
1.8 1.6 1.4
ERROR - dB(10mV/dB)
0.5 0.4 0.3 10 A 0.2 0.1 0 -0.1 -0.2 10nA -0.3 -0.4 10n 100n 1 10 IPD - A 100 1m 10m -0.5 1n 10n 100n 1 10 IPD - A 100 1m 10m 100nA 1A 100 A 1mA
1.2
VLOG - V
1.0 0.8 0.6 0.4 0.2 0 1n
10nA 100nA 1A 10 A 100mA 1mA
TPC 3. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
TPC 6. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA)
-4-
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AD8305
1.8 1.6 1.4
ERROR - dB(10mV/dB)
0.5 0.4 10nA 0.3 10 A 0.2 0.1 0 -0.1 -0.2 100 A -0.3 -0.4 10n 100n 1 10 IREF - A 100 1m 10m -0.5 1n 10n 100n 1 10 IREF - A 100 1m 10m 1mA 100nA 1A
1.2
VLOG - V
1.0 0.8 0.6 0.4 0.2 0 1n 1mA 100 A 10 A 1A 100nA 10nA
TPC 7. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA)
TPC 10. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA)
0.5 +3V, 0V 0.4 +5V, 0V 0.3 +9V, 0V
ERROR - dB(10mV/dB)
1.4
+12V, 0V
1.2 100 A TO 1mA: T-RISE = <1 s, T-FALL = < 1 s 1.0 10 A TO 10 A: T-RISE = <1 s, T-FALL = < 1 s
VOUT - V
0.2 0.1 0 -0.1 +3V, -0.5V -0.2 +5V, -5V -0.3
0.8 1 A TO 10 A: T-RISE = 1 s, T-FALL = 5 s 0.6 100nA TO 1 A: T-RISE = 5 s, T-FALL = 20 s 0.4 10nA TO 100nA: T -RISE = 20 s, T-FALL = 30 s 0.2
-0.4 -0.5 1n 10n 100n 1 10 IPD - A 100 1m 10m
0 -20 0 20 40 60 80 100 120 140 160 180
TIME - s
TPC 8. Law Conformance Error vs. IPD for Various Supply Conditions (see Annotations)
TPC 11. Pulse Response - IPD to VOUT (G = 1)
0.4 0.3 0.2
1.6 1.4 1.2 1.0 100nA TO 1 A: T-RISE = 30 s, T-FALL = 5 s 1 A TO 10 A: T-RISE = 5 s, T-FALL = < 1 s 10 A TO 100 A: T-RISE = 1 s, T-FALL = < 1 s 0.6 0.4 0.2 0 -20 100 A TO 1mA: T -RISE = < 1 s, T-FALL = < 1 s
10nA TO 100nA: T-RISE = 30 s, T-FALL = 20 s
VSUM - V INPT - mV
0.1
VOUT - V
0 -0.1 -0.2 -0.3 -0.4 1n
0.8
10n
100n
1
10 IPD - A
100
1m
10m
0
20
40
60
80 100 TIME - s
120
140
160
180
TPC 9. VINPT - VSUM vs. IPD
TPC 12. Pulse Response - IREF to VOUT (G = 1)
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-5-
AD8305
10 10nA 3 100nA 10 A 100 A -10
NORMALIZED RESPONSE - dB
0
0 AV = 1
-3 AV = 2 AV = 5 -6 AV = 2.5 -9
VOUT
-20 1mA -30 1A -40
-50 100
1k
10k 100k 1M FREQUENCY - Hz
10M
100M
-12 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 13. Small Signal AC Response (5% Sine Modulation), from IPD to VOUT (G = 1) for IPD in Decade Steps from 10 nA to 1 mA, IREF = 10A
TPC 16. Small Signal AC Response of the Buffer for Various Closed-Loop Gains (RL = 1 k CL < 2 pF)
10 10nA 100nA 0 10 A
2.0 1.5
100 A
NORMALIZED RESPONSE - dB
1.0 VOS DRIFT - mV
-10
MEAN + 3 0.5 0 -0.5 MEAN - 3 -1.0 -1.5
-20 1mA -30 1A -40
-50 100
1k
10k 100k 1M FREQUENCY - Hz
10M
100M
-2.0 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE - C
TPC 14. Small Signal AC Response (5% Sine Modulation), from IREF to VOUT (G = 1) for IREF in Decade Steps from 10 nA to 1 mA, IPD = 10A
TPC 17. Buffer Input Offset Drift vs. Temperature (3 to Either Side of Mean)
100 10nA
6
5
10 100nA
Vrms/ Hz mVrms
4
1 1A 10 A
3
2
0.1 100 A
1
0.01 100
1k
10k 100k FREQUENCY - Hz
1M
10M
0 100
1k
10k
100k IPD - A
1M
10M
100M
TPC 15. Spot Noise Spectral Density at VOUT (G = 1) vs. Frequency for IPD in Decade Steps from 10 nA to 1 mA
TPC 18. Total Wideband Noise Voltage at VOUT vs. IPD (G = 1)
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AD8305
2.0 TA = 25 C 1.5 1.0 0.5 0 MEAN - 3 -0.5 -1.0 -1.5 -2.0 1n MEAN + 3
20 15 10
VREF DRIFT -mV
ERROR - dB(10mV/dB)
5 0 -5 -10 -15 -20 -25 -40 -30 -20 -10
MEAN + 3
MEAN - 3
10n
100n
1
10 IPD - A
100
1m
10m
0
10
20
30
40
50
60
70
80
90
TEMPERATURE - C
TPC 19. Law Conformance Error Distribution (3 to Either Side of Mean)
TPC 22. VREF Drift vs. Temperature (3 to Either Side of Mean)
2.0 TA = 0 C, 70 C 1.5 1.0 MEAN + 3 @ 70 C
20 15 10
ERROR - dB(10mV/dB)
0 -0.5 -1.0 MEAN - 3 @ 70 C -1.5 -2.0 MEAN 3 @0C
DRIFT - mV
0.5
5 0 -5
MEAN + 3
MEAN - 3 -10 -15 -20 -40 -30 -20 -10
1n
10n
100n
1 IPD - A
10
100
1m
10m
0
10
20
30
40
50
60
70
80
90
TEMPERATURE - C
TPC 20. Law Conformance Error Distribution (3 to Either Side of Mean)
TPC 23. VREF - VIREF Drift vs. Temperature (3 to Either Side of Mean)
4 TA = -40 C, +85 C 3 MEAN + 3 @ -40 C 2
5 4 3 2 VINPT DRIFT - mV
ERROR - dB(10mV/dB)
1 MEAN 0 -1 -2 3 @ +85 C
1 MEAN + 3 0 -1 -2 MEAN - 3 -3
-3 -4 1n
MEAN - 3 @ -40 C
-4
10n
100n
1
10 IPD - A
100
1m
10m
-5 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE - C
TPC 21. Law Conformance Error Distribution (3 to Either Side of Mean)
TPC 24. VINPT Drift vs. Temperature (3 to Either Side of Mean)
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AD8305
10 8 6
3000 4000 3500
Vy DRIFT - mV/dec
4 MEAN + 3 2 0 -2 MEAN - 3 -4 -6 -8
1000 500 0 0.4 2500
COUNT
0 10 20 30 40 50 TEMPERATURE - C 60 70 80 90
2000 1500
-10 -40 -30 -20 -10
0.6
0.8
1.0 1.2 INTERCEPT - nA
1.4
1.6
TPC 25. Slope Drift vs. Temperature (3 to Either Side of Mean of 200 mV/decade)
TPC 28. Distribution of Logarithmic Intercept (Nominally 1nA when RREF = 200 k 0.1%) Sample >22,000
350
7000 6000
250 MEAN + 3 150 Iz DRIFT - pA
5000 4000 3000
-50
COUNT
50
-150 MEAN - 3 -250 -350 -40 -30 -20 -10
2000
1000
0
10 20 30 40 50 TEMPERATURE - C
60
70 80 85 90
0 2.44
2.46
2.48
2.50 VREF - V
2.52
2.54
2.56
TPC 26. Intercept Drift vs. Temperature (3 to Either Side of Mean of 1 nA)
TPC 29. Distribution of VREF (RL = 100 k) Sample >22,000
6000
6000
5000
5000
4000
4000
COUNT
3000
COUNT
195 200 SLOPE - mV/dec 205 210
3000
2000
2000
1000
1000
0 190
0 -0.015
-0.010
-0.005 0.0 0.005 VINPT - VSUM VOLTAGE - V
0.010
0.015
TPC 27. Distribution of Logarithmic Slope (Nominally 200 mV/decade) Sample >22,000
TPC 30. Distribution of Offset Voltage (VINPT - VSUM) Sample >22,000
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AD8305
GENERAL STRUCTURE
The AD8305 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 1 is a simplified schematic showing the key elements.
BIAS GENERATOR PHOTODIODE 2.5V INPUT CURRENT 80k I 0.5V
PD
billion between -35C and +85C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the second operating at a reference current IREF, can be written as:
IREF I
REF
V
BE1
VREF 20k COMM 0.5V
V
- BE2 (SUBTRACT AND
TEMPERATURE COMPENSATION DIVIDE BY T K
VBE1 - VBE2 = kT /q In(IC /IS ) - kT /q In(IREF /IS ) = In (10) kT /q log10 (IPD /IREF ) = 59.5 mV log10 (IPD /IREF ) (T = 300 K )
(2)
VSUM INPT
44 A/dec 14.2k VRDZ 451 VLOG
0.5V Q1 V BE1 Q2 V BE2 6.69k
The uncertain and temperature-dependent saturation current IS, which appears in Equation 1, has thus been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage-mode to currentmode, is an intermediate, temperature-corrected current: ILOG = IY log10 (IPD /IREF ) (3) where IY is an accurate, temperature-stable scaling current that determines the slope of the function (the change in current per decade). For the AD8305, IY is 44 A, resulting in a temperatureindependent slope of 44 A/decade, for all values of IPD and IREF. This current is subsequently converted back to a voltagemode output, VLOG, scaled 200 mV/decade. It is apparent that this output should be zero for IPD = IREF, and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. However, it is impractical to use such a small reference current as 1 nA. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when pin VRDZ is directly connected to VREF. This has the effect of moving the intercept to the left by four decades, from 10 A to 1 nA: ILOG = IY log10 (IPD /IINTC ) (4) where IINTC is the operational value of the intercept current. To disable this offset, pin VRDZ should be grounded, then the intercept IINTC is simply IREF. Since values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 k, formed by the parallel combination of a 6.69 k resistor to ground and the 14.2 k resistor to the VRDZ pin. When the VLOG pin is unloaded and the intercept repositioning is disabled by grounding VRDZ, the output current ILOG generates a voltage at the VLOG pin of: VLOG = I LOG x 4.55 k
= VY log10 (I PD /I REF ) = 44 A x 4.55 k x log10 (I PD /I REF )
COMM VNEG (NORMALLY GROUNDED)
Figure 1. Simplified Schematic
The photodiode current I PD is received at pin INPT. The voltage at this node is essentially equal to those on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts the input current IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of V SUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, that is, one fifth of the reference voltage of 2.5 V appearing on pin VREF. The resistance at the VSUM pin is nominally 16 k; this voltage is not intended as a general bias source. The AD8305 also supports the use of an optional negative supply voltage, VN , at pin VNEG. When VN is -0.5 V or more negative, VSUM may be connected to ground; thus INPT and IREF assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating will cause errors at large input currents. The input dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is generated externally, to a recommended value of 10 A. However, other values over a several-decade range can be used with a slight degradation in law conformance (TPC 1).
Theory
(5)
The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by the following equation, which immediately shows its basic logarithmic nature: VBE = kT /qIn(I C /I S ) (1) where IC is its collector current, IS is a scaling current, typically only 10-17 A, and kT/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 25.85 mV at 300 K. The current, IS, is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a REV. 0 -9-
where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive loading on VLOG will lower this slope and also result in an overall scaling uncertainty due to the variability of the on-chip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = -0.5 V or larger, the input pins INPT and IREF may now be positioned at ground level by simply grounding VSUM.
AD8305
Managing Intercept and Slope
+5V VPOS VRDZ VREF 200k 0.5V IREF 20k 80k 2.5V BIAS GENERATOR
When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire five-decade input current range. As noted previously, this introduces an accurate offset voltage of 0.8 V at the VLOG pin, equivalent to four decades, resulting in a logarithmic transfer function that can be written as:
0.5 log 10
()
PD
I
1nA
VOUT
12k 8k
VLOG = VY log10 10 x IPD /IREF
4
= VY log10 (IPD /IINTC )
(
)
COMM V BE2 Q2 Q1 - + SCAL 14.2k BFIN
(6)
VBIAS
1k 1nF I PD INPT
I TEMPERATURE LOG 451 COMPENSATION 6.69k COMM
VLOG CFLT 10nF
where IINTC = IREF /104 Thus, the effective intercept current I INTC is only one tenthousandth of IREF, corresponding to 1 nA when using the recommended value of IREF = 10 A. The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged, in view of the fact that the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would want to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer, which is provided to avoid such miscalibration and also allow higher slopes to be used. The AD8305 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load-driving capabilities and a unity-gain bandwidth of >12 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage VY, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. Further details of these can be found in the AD8304 data sheet.
Response Time and Noise Considerations
V BE1 0.5V
1k
VSUM 1nF 1nF
VNEG
COMM
Figure 2. Basic Connections for Fixed Intercept Use
The 2 V difference in voltage between the VREF and INPT pins in conjunction with the external 200 k resistor RREF provide a reference current IREF of 10 A into Pin IREF. Connecting pin VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively lowering the intercept current IINTC by a factor of 104 to position it at 1 nA. A wide range of other values for IREF, from under 100 nA to over 1 mA, may be used. The effect of such changes is shown in TPC 3. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of IREF. In fixedintercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, here shown as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and help to provide a clean reference current. Since the basic scaling at VLOG is 0.2 V/decade, and thus a swing of 4 V at the buffer output would correspond to 20 decades, it will often be useful to raise the slope to make better use of the railto-rail voltage range. For illustrative purposes, the circuit in Figure 2 provides an overall slope of 0.5 V/decade (25 mV/dB). Thus, using IREF = 10 A, VLOG runs from 0.2 V at IPD = 10 nA to 1.4 V at IPD = 1 mA while the buffer output runs from 0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB (electrical, that is, 60 dB optical power). The optional capacitor from VLOG to ground forms a singlepole low-pass filter in combination with the 4.55 k resistance at this pin. For example, using a CFLT of 10 nF the -3 dB corner frequency is 3.5 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8304 data sheet.
The response time and output noise of the AD8305 are fundamentally a function of the signal current IPD. For small currents, the bandwidth is proportional to IPD, as shown in TPC 13. The output low frequency voltage-noise spectral-density is a function of IPD (TPC 15) and also increases for small values of I REF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 Data Sheet.
APPLICATIONS
The AD8305 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent, which is represented in decibel terms. Basic connections for measuring a single-current input are shown in Figure 2, which also includes various nonessential components, as will be explained.
-10-
REV. 0
AD8305
The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 2 will usually suffice, but some experimentation may be necessary when the photodiode capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (<100 nA) and temperature (<0C). Modifying the RC network to 4.7 nF and 2 k will allow operation to -40C at 10 nA. By inspecting the transient response to perturbations in IREF at representative current levels, the capacitor value can be adjusted to provide fast rise and fall times with acceptable settling. To fine tune the network zero, the resistor value should be adjusted.
CALIBRATION
The Uncalibrated Error line in Figure 3 was generated assuming that the slope of the measured output was 200 mV/decade when in fact it was actually 194 mV/decade. Correcting for this discrepancy decreased measurement error up to 3 dB.
USING A NEGATIVE SUPPLY
Most applications of the AD8305 require only a single supply of 3.0 V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure 4.
5V VPOS VRDZ VREF RREF 200k 0.5V IREF VBIAS 1k 1nF I PD INPT 1k 1nF VSUM 0.5V + V F - R S V N VNEG V -0.5V NEG C1 V -V N F R S I +I q SIGMAX Q2 Q1 20k 80k 2.5 V I PD 0.5 log 10 1nA VOUT BIAS GENERATOR
()
12k 8k
COMM V BE2 - + SCAL 14.2k BFIN 451
The AD8305 has a nominal slope and intercept of 200 mV/decade and 1 nA, respectively. These values are untrimmed and the slope alone may vary as much as 7.5% over temperature. For this reason it is recommended that a simple calibration be done to achieve increased accuracy.
1.4 UNCALIBRATED ERROR 1.2 3 4
I TEMPERATURE LOG COMPENSATION 6.69k COMM
VLOG CFLT 10nF
V BE1
I +I q SIG
COMM
I =I +I SIG PD REF
ERROR - dB(10mV/dB)
1.0 MEASURED OUTPUT
VLOG - V
2 1 0 CALIBRATED ERROR -1 IDEAL OUTPUT
Figure 4. Negative Supply Application
0.8
0.6
0.4
0.2
-2 -3 1.E-02
0 1.E-09
1.E-08
1.E-07
1.E-06 1.E-05 IPD - A
1.E-04
1.E-03
Figure 3. Using Two-Point Calibration to Increase Measurement Accuracy
The use of a negative supply, VN, allows the summing node to be placed at ground level whenever the input transistor (Q1 in Figure 1) has a sufficiently negative bias on its emitter. When VNEG = -0.5 V, the VCE of Q1 and Q2 will be the same as for the default case when VSUM is grounded. This bias need not be accurate, and a poorly defined source can be used. The source does however need to be able to support the quiescent current as well as the INPT and IREF signal current. For example, it may be convenient to utilize a forward-biased junction voltage of about 0.7 V or a Schottky barrier voltage of a little over 0.5 V. The effect of supply on the dynamic range and accuracy can be seen in TPC 8. With the summing node at ground, the AD8305 may now be used as a voltage-input log amp at either the numerator input, INPT, or the denominator input, IREF, by inserting a suitably scaled resistor from the voltage source to the relevant pin. The overall accuracy for small input voltages is limited by the voltage offset at the inputs of the JFET op amps. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of IPD. However, the voltage VLOG remains referenced to the ACOM pin, and while it does not swing negative for default operating conditions, it is free to do so. Thus, adding a resistor from VLOG to the negative supply lowers all values of VLOG, which raises the intercept. The disadvantage of this method is that the slope is reduced by the shunting of the external resistor, and the poorly defined ratio of on-chip and off-chip resistances causes errors in both the slope and the intercept.
Figure 3 shows the improvement in accuracy when using a twopoint calibration method. To perform this calibration, apply two known currents I1 and I2, in the linear operating range between 10 nA and 1 mA. Measure the resulting output V1 and V2, respectively, and calculate the slope m and intercept b.
m = (V1 - V2 ) / log10 ( I1 ) - log10 ( I 2 )
b = V1 - m x log10 ( I1 )
[
]
(7) (8)
The same calibration could be performed with two known optical powers, P1 and P2. This allows for calibration of the entire measurement system while providing a simplified relationship between the incident optical power and VLOG voltage. m = (V1 - V2 ) / (P1 - P2 ) b = V1 - m x P1 REV. 0 (9) (10)
-11-
AD8305
+5V VPOS VRDZ VREF P REF 1nF REFERENCE DETECTOR 1k IREF I +5V I SIGNAL DETECTOR P SIG 1k
PD REF
VOUT 80k 20k 0.5V COMM V Q2 Q1 - + V SCAL 14.2k BFIN 12.1k I TEMPERATURE LOG 451 COMPENSATION VLOG
BE1 BE2
BIAS 2.5 V GENERATOR
44.2k 28.0k 33nF
I PD 0.5 log 10 I 18nF
()
REF
+2
INPT 0.5V VNEG
6.69k COMM COMM
VSUM 1nF
Figure 5. Optical Absorbance Measurement
LOG-RATIO APPLICATIONS
It is often desirable to determine the ratio of two currents, for example, in absorbance measurements. These are commonly used to assess the attenuation of a passive optical component, such as an optical filter or variable optical attenuator. In these situations, a reference detector is used to measure the incident power entering the component. The exiting power is then measured using a second detector and the ratio is calculated to determine the attenuation factor. Since the AD8305 is fundamentally a ratiometric device, having nearly identical logging systems for both numerator and denominator (IPD and IREF, respectively), it can greatly simplify such measurements. Figure 5 illustrates the AD8305's log-ratio capabilities in optical absorbance measurements. Here a reference detector diode is used to provide the reference current, IREF, proportional to the optical reference power level. A second detector measures the transmitted signal power, proportional to IPD. The AD8305 calculates the logarithm of the ratio of these two currents, as shown in Equation 11, and which is reformulated in power terms in Equation 12. Both of these equations include the internal factor of 10,000 introduced by the output offset applied to VLOG via pin VRDZ. If the true (nonoffset) log ratio shown in Equation 4 is preferred, VRDZ should be grounded to remove the offset. As already noted, the use of a negative supply at pin VNEG will allow both VLOG and the buffer output to swing below ground, and also allow the input pins INPT and IREF to be set to ground potential. Thus, the AD8305 may also be used to determine the log ratio of two voltages. Figure 5 also illustrates how a second-order Sallen-Key low-pass filter can be realized using two external capacitors and one resistor. Here, the corner frequency is set to 1 kHz and the filter Q is chosen to provide an optimally flat (overshoot-free) pulse response. To scale this frequency either up or down, simply scale the capacitors by the appropriate factor. Note that one of the resistors needed to realize this filter is the output resistance of 4.55 k present at pin VLOG. While this will not ratio
exactly to the external resistor, which may slightly alter the Q of the filter, the effect on pulse response will be negligible for most purposes. Note that the gain of the buffer ( 2.5) is an integral part of this illustrative filter design; in general, the filter may be redesigned for other closed-loop gains. The transfer characteristics can be expressed in terms of optical power. If we assume that the two detectors have equal responsivities, the relationship is:
VOUT = 0.5V log10 10 4 x PSIG /PREF
(
)
(11)
Using the identity log10(AB) = log10A + log10B and defining the attenuation as -10 log10(PSIG / PREF), the overall transfer characteristic can be written as: VOUT = 2 - 50mV /dB x where = -10 x log10 (PSIG PREF ) Figure 6 illustrates the linear-in-dB relationship between the absorbance and the output of the circuit in Figure 5.
2.5
(12)
2.0
1.5
VLOG - V
1.0
0.5
0 0 5 10 15 20 25 30 35 ATTENUATION - dB 40 45 50
Figure 6. Example of an Absorbance Transfer Function
-12-
REV. 0
AD8305
REVERSING THE INPUT POLARITY
Some applications may require interfacing to a circuit that sources current rather than sinks current, such as connecting to the cathode side of a photodiode. Figure 7 shows the use of a current mirror circuit. This allows for simultaneous monitoring of the optical power at the cathode, and a data recovery path using a transimpedance amplifier at the anode. The modified Wilson mirror provides a current gain very close to unity and a high output resistance. Figure 8 shows measured transfer function and law conformance performance of the AD8305 in conjunction with this current mirror interface.
5V 0.1 F
16 15 14 13
These measures are needed to minimize the risk of leakage current paths. With 0.5 V as the nominal bias on the INPT pin, a leakage-path resistance of 1 G to ground would subtract 0.5 nA from the input, which amounts to an error of -0.44 dB for a source current of 10 nA. Additionally, the very high output resistance at the input pins and the long cables commonly needed during characterization allow 60 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reduce the pickup of these spurious signals.
VREF KIETHLEY 236 IREF VNEG VPOS VOUT BFIN VLOG
AD8305
CHARACTERIZATION BOARD
VOUT = .200 log10 (I PD/1nA)
COMM COMM COMM COMM MAT03
1
KIETHLEY 236
OUTPUT
INPT VSUM
VRDZ
VOUT 12
2.5V
2
VREF
SCAL 11
MAT03
200k 1nF
0V
AD8305
3
IREF
BFIN 10 VLOG 9
TRIAX CONNECTORS (SIGNAL - INPT AND IREF GUARD - VSUM SHIELD - GROUND)
DC MATRIX/DC SUPPLIES/DMM
0V IPD 1k 1nF IIN I PD 10nA TO 1mA
4
INPT
VSUM VNEG VNEG VPOS
5 6 7 8
0.1 F 5V TIA DATA PATH
Figure 7. Wilson Current Mirror for Cathode Interfacing
1.6 1.4 1.2 1.0
VLOG - V
1.0 0.75 0.5 5V 0.25 0 3V -0.25 5V -0.5 3V 5V -0.75 5V -1.0 1.E-02
Figure 9. Primary Characterization Setup The primary characterization setup shown in Figure 9 is used to measure VREF, the static (dc) performance, logarithmic conformance, slope and intercept, the voltages appearing at pins VSUM, INPT and IREF, and the buffer offset and VREF drift with temperature. To ensure stable operation over the full current range of IREF and temperature extremes, filter components of C1 = 4.7 nF and R13 = 2 k are used at pin to IREF ground. In some cases, a fixed resistor between pins VREF and IREF was used in place of a precision current source. For the dynamic tests, including noise and bandwidth measurements, more specialized setups are required.
HP 3577A NETWORK ANALYZER OUTPUT INPUT R INPUT A INPUT B
0.8 0.6 0.4 0.2 0 1.E-09
ERROR - dB(10mV/dB)
+IN AD8138 B EVALUATION BOARD A AD8138 PROVIDES DC OFFSET
BNC-T
16
15
14
13
COMM COMM COMM COMM 1.E-06 1.E-05 IPD - A 1.E-04 1.E-03
1
1.E-08
1.E-07
VRDZ
VOUT 12
Figure 8. Log Output and Error using Current Mirror with Various Supplies
CHARACTERIZATION METHODS
2
VREF
SCAL 11
AD8305
3
IREF
BFIN 10 VLOG 9
4
INPT
During the characterization of the AD8305, the device was treated as a precision current-input logarithmic converter, since it is not practical for several reasons to generate accurate photocurrents by illuminating a photodiode. The test currents were generated either by using well calibrated current sources, such as the Keithley 236, or by using a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM. REV. 0
VSUM VNEG VNEG VPOS
5 6 7 8
+VS 0.1 F
Figure 10. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 10 shows the configuration used to measure the buffer amplifier bandwidth. The AD8138 evaluation board includes -13-
AD8305
provisions to offset VLOG at the buffer input, allowing measurements over the full range of IPD using a single supply. The network analyzer input impedances were set to 1 M.
HP 3577A NETWORK ANALYZER OUTPUT INPUT R INPUT A INPUT B
The configuration in Figure 12 is used to measure the noise performance. Batteries provide both the supply voltage and the input current in order to minimize the introduction of spurious noise and ground loop effects. The entire evaluation system, including the current setting resistors, is mounted in a closed aluminum enclosure to provide additional shielding to external noise sources.
LECROY 9210 CH A 9213 TDS5104 CH1
POWER SPLITTER
1
16
15
14
13
COMM COMM COMM COMM VRDZ VOUT 12
2
VREF
SCAL 11
1nF R2
3
AD8305
IREF BFIN 10
1 4
16
15
14
13
COMM COMM COMM COMM VRDZ VOUT 12
+IN AD8138 B EVALUATION BOARD A
1k R1 1k 1nF
INPT
VLOG 9
2
VSUM VNEG VNEG VPOS
5 6 7 8
VREF
SCAL 11
200k
3
AD8305
IREF BFIN 10 VLOG 9
+VS 0.1 F
1nF 1k R1 1k 1nF
4
INPT
VSUM VNEG VNEG VPOS
5 6 7 8
Figure 11. Configuration for Logarithmic Amplifier Bandwidth Measurement
The setup shown in Figure 11 was used for frequency response measurements of the logarithmic amplifier section. The AD8138 output is offset to 1.5 V dc and modulated to a depth of 5% at frequency. R1 is chosen (over a wide range of values up to 1.0 G) to provide IPD. The buffer was used to deload VLOG from the measurement system.
HP 89410A
+VS 0.1 F
Figure 13. Configuration for Logarithmic Amplifier Pulse Response Measurement
SOURCE
TRIGGER
CHANNEL 1 CHANNEL 2
Figure 13 shows the setup used to make the pulse response measurements. As with the bandwidth measurement, the VLOG is connected directly to BFIN and buffer amplifier is configured for unity gain. The buffer's output is connected through a short cable to the TDS5104 scope with input impedance set to 1 M. The LeCroy's output is offset to create the initial pedestal current for a given value of R1, the pulse then creates one-decade current step.
EVALUATION BOARD
16
15
14
13
COMM COMM COMM COMM
1
VRDZ
VOUT 12
An evaluation board is available for the AD8305, the schematic for which is shown in Figure 16. It can be configured for a wide variety of experiments. The buffer gain is factory-set to unity, providing a slope of 200 mV/decade, and the intercept is set to 1 nA. Table I describes the various configuration options.
2
VREF
SCAL 11
1nF 200k
3
AD8305
IREF BFIN 10 VLOG 9
ALKALINE "D" CELL + -
1k R1 1k 1nF
4
INPT
VSUM VNEG VNEG VPOS
5 6 7 8
ALKALINE "D" CELL 0.1 F + - + - + -
Figure 12. Configuration for Noise Spectral Density Measurement
-14-
REV. 0
AD8305
Table I. Evaluation Board Configuration Options
Component P1 P2, R8, R9, R10, R11, R17, R18
Function
Default Condition
Supply Interface. Provides access to supply pins, VNEG, COMM, and VPOS. P1 = Installed Monitor Interface. By adding 0 resistors to R8, R9, R10, R11, R17, and R18, P2 = Not Installed the VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored R8 = R9 = R10 = Open (Size 0603) using a high impedance probe. R17 = R18 = Open (Size 0603) R2 = R6 = 0 (Size 0603) R3 = R4 = Open (Size 0603) R11 = R14 = 0 (Size 0603) C2 = C7 = Open (Size 0603) C9 = C10 = Open (Size 0603) VLOG = VOUT = Installed
R2, R3, R4, R6, R14, Buffer Amplifier/Output Interface. The logarithmic slope of the AD8305 C2, C7, C9, C10 can be altered using the buffer's gain-setting resistors, R2 and R3. R4, R14, and C2 allow variation in the buffer loading. R6, C7, C9, and C10 are provided for a variety of filtering applications.
R1, R7, R19, R20
Intercept Adjustment. The voltage dropped across resistor R1 determines the R1 = 200 k (Size 0603) intercept reference current, nominally set to 10 A using a 200 k 1% resistor. R7 = R19 = 0 (Size 0603) R7 and R19 can be used to adjust the output-offset voltage at the VLOG output. R20 = Open (Size 0603) Supply Decoupling C3 = C4 = 0.01 F (Size 0603) C5 = C6 = 0.1 F (Size 0603) R12 = R15 = 0 (Size 0603) C11 = 1 nF (Size 0603) R13 = R16 = 1 k (Size 0603) C1 = C8 = 1 nF (Size 0603)
R12, R15, C3, C4, C5, C6
C11 R13, R16, C1, C8 IREF, INPT, PD, LK1, R5
VSUM Decoupling Capacitor Input Compensation. Provides essential HF compensation at the input pins, INPT and IREF.
Input Interface. The test board is configured to accept a current through the IREF = INPT = Installed SMA connector labeled INPT. An SC-style packaged photodiode can be PD = Not Installed used in place of the INPT SMA for optical interfacing. By removing R1 and LK1 = Installed adding a 0 short for R5, a second current can be applied to the IREF input R5 = Open (Size 0603) (also SMA) for evaluating the AD8305 in log-ratio applications. SC-Style Photodiode. Allows for direct mounting of SC style photodiodes. J1 = Not Installed
J1
Figure 14. Component Side Layout
Figure 15. Component Side Silkscreen
REV. 0
-15-
AD8305
16 R20 OPEN VRDZ R17 OPEN R18 OPEN R5 OPEN R13 1k I PD
1 2
15 COMM
14 COMM
13 COMM VOUT 12 R2 0 R3 OPEN R6 C10 OPEN 0 C2 OPEN C9 OPEN R8
R10 OPEN
VOUT
COMM 1 VRDZ
R14 0 R4 OPEN
VOUT
VREF
R19 R1 200k 1% 0 I REF
2
VREF
SCAL
11
AD8305
3 IREF BFIN 10
IREF
VLOG
OPEN R11
4
INPT VSUM 5 VNEG 6 VNEG 7
VLOG VPOS 8
9 C7 OPEN
VLOG
C1
1nF
0
SC-STYLE PD
3
VRDZ
1
INPT C3 0.01 F LK1 C11 1nF R9 OPEN C8 VSUM 1nF C6 0.1 F
AGND VNEG
C4 0.01 F R15 0 R12 0 C5 0.1 F
AGND
2
R16 1k
VOUT
3
VREF
4
1
2
3 P1
VPOS
VSUM
5
VLOG
6
P2
Figure 16. Evaluation Board Schematic
OUTLINE DIMENSIONS 16-Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body (CP-16)
Dimensions shown in millimeters
0.50 0.40 0.30 PIN 1 INDICATOR
1 2
3.00 BSC SQ 0.45 PIN 1 INDICATOR
TOP VIEW
0.60 MAX
2.75 BSC SQ 0.50 BSC
BOTTOM VIEW
1.45 1.30 SQ 1.15 0.25 MIN
12 MAX 1.00 0.90 0.80 SEATING PLANE 0.30 0.23 0.18
0.80 MAX 0.65 NOM 0.05 MAX 0.01 NOM 0.20 REF
1.50 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
-16-
REV. 0
PRINTED IN U.S.A.
C03053-0-11/02(0)
R7 0

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